| Date |
Time |
Component |
Description |
|
| 04/20/2011 | 16:47:00 | AIP1 | NOAA-18 STX2 was configured for both AIP & TIP Bi-Phase to verify FCDAS ability to receive real-time AIP data. |
|
| 08/19/2010 | 13:21:45 | MIU | Slow Dump the MIU Exception Log |
|
| 08/19/2010 | 13:20:37 | MIU | Slow Dump the MIU Interrupt Log |
|
| 08/19/2010 | 13:19:23 | MIU | Reset the MIU AIP FIFO |
|
| 08/19/2010 | 13:19:23 | MIU | The MIU AIP FIFO Register was reset and AIP telemetry is flowing correctly. |
|
| 08/18/2010 | 21:48:56 | MIU | Slow Dump of MIU Interrupt Log - Unsuccessful, AIP FIFO problems |
|
| 08/17/2010 | 20:23:53 | MIU | The MIU experienced an anomaly during the N18 MIMU Reduced Gyro Test #2. |
|
| 06/28/2010 | 18:57:00 | XSU1 | STX4's configuration cleared to conclude NOAA-18 McMurdo telemetry reception and command test in preparation for upcoming NOAA-18 MIMU tests. |
|
| 01/24/2008 | 13:51:24 | | Applies 1-sec dwell to the Main Bus Voltage. |
|
| 07/11/2007 | 17:55:00 | TIP1 | TOAR 447 invesitgation. Pitch oscillation test. Dwell on NSADBDPY to determine if Solar Array boom wiggle" exists and is influencing pitch." |
|
| 11/08/2006 | 17:25:30 | TIP1 | Returns TIP and DDRs to nominal orbital mode. |
|
| 11/08/2006 | 12:24:20 | TIP2 | Dwell on analog channel 292 (DDR1 current, NDDR1I) |
|
| 11/08/2006 | 12:24:20 | TIP1 | Dwell on analog channel 292 (DDR1 current, NDDR1I) |
|
| 11/08/2006 | 10:37:00 | TIP1 | Dwell on analog channel 340 (DDR4 current, NDDR4I) |
|
| 11/08/2006 | 03:48:30 | TIP2 | Dwell on analog channel 308 (DDR2 current, NDDR2I) |
|
| 10/06/2006 | 21:51:00 | TIP1 | TIP dwell back to 1 sec bus voltage |
|
| 10/06/2006 | 18:21:00 | TIP1 | TIP (1 sec) dwell on NTCE2H ch 27 |
|
| 10/06/2006 | 18:20:00 | TIP1 | TIP dwell back to 1 sec bus voltage |
|
| 10/05/2006 | 15:12:00 | TIP1 | TIP (1 sec) dwell on NTCE2H ch 217 |
|
| 02/23/2006 | 19:41:47 | TIP1 | Dwell on analog channel 153 (bus voltage) |
|
| 02/23/2006 | 16:25:08 | TIP1 | Dwell on analog channel 457 (SARR 406 side A AGC NSARA4G) |
|
| 01/27/2006 | 19:33:00 | XSU1 | Deconfigure STX4 |
|
| 01/27/2006 | 19:26:00 | XSU1 | Configure STX4 for AIP/TIP |
|
| 11/15/2005 | 18:16:00 | DDR5A | Stop Rec 5A |
|
| 11/15/2005 | 18:15:00 | DDR5A | Play SAIP at 2.66 Mbps |
|
| 11/15/2005 | 18:14:00 | XSU1 | Configure XSU - Rec 5 to SBand 2 |
|
| 11/15/2005 | 18:13:00 | DDR5A | Stop Rec 5A |
|
| 11/15/2005 | 18:12:00 | DDR5A | Send Rec 5A to EOF |
|
| 11/15/2005 | 18:11:00 | DDR5A | Stop Rec 5A |
|
| 11/15/2005 | 18:10:00 | DDR5B | Stop Rec 5B |
|
| 11/04/2005 | 23:39:00 | DDR3A | Stop Rec 3A |
|
| 11/04/2005 | 23:38:00 | DDR3A | Play STIP at 2.66 Mbps |
|
| 11/04/2005 | 23:37:00 | DDR3A | Stop Rec 3A |
|
| 11/04/2005 | 23:36:00 | DDR3A | Send Rec 3A to End Of File |
|
| 11/04/2005 | 23:35:00 | DDR3A | Stop Rec 3A |
|
| 09/22/2005 | 17:20:00 | | Deconfigure and turn off STX 4, restore nominal analog dwell channel, remove MIMU raw telemetry from the 1 sec table, backup CPU, and remove SADTRUE on control SCP. |
|
| 09/21/2005 | 17:30:00 | | Deconfigure and turn off STX 4, restore nominal analog dwell channel. Day 1 slew test ends |
|
| 09/20/2005 | 18:00:00 | XSU1 | Clear STX4 Config |
|
| 09/20/2005 | 18:00:00 | AIP | Config AIP for AIP Data Mode (TIP/AMSU/MHS Data) |
|
| 09/20/2005 | 16:00:00 | AIP | Configure AIP for Tip Bi-phase data mode (Tip Data Only) |
|
| 09/20/2005 | 16:00:00 | XSU1 | Configure XSU for AIP/TIP |
|
| 09/12/2005 | 14:12:00 | XSU1 | Clear STX4 Configuration |
|
| 09/12/2005 | 12:33:00 | XSU | Configure STX4 for AIP |
|
| 08/22/2005 | 17:32:00 | | Configure TIP to normal operational mode |
|
| 08/22/2005 | 17:30:00 | | Configure for High Speed Dwell on HIRS filter wheel motor current |
|
| 08/11/2005 | 14:40:00 | MIRP | Select AVHRR channel 2 for APT channel A and select AVHRR channel 4 for APT channel B. All other MIRP settings will remain the same. |
|
| 08/10/2005 | 17:55:00 | | 1 sec analog dwell on NSADPOS2 |
|
| 08/10/2005 | 14:45:00 | | 1 sec analog dwell on NSADPOS1 |
|
| 07/27/2005 | 12:05:00 | | 1-sec Analog dwell on patch current |
|
| 07/12/2005 | 17:45:00 | | Restore nominal dwell channel |
|
| 07/12/2005 | 17:43:00 | | Dwell on HIRS FW motor Current |
|
| 07/12/2005 | 16:20:00 | | Dwell on HIRS Scan Motor Current |
|
| 07/12/2005 | 12:56:00 | | Dwell on HIRS FW motor current |
|
| 07/11/2005 | 21:30:00 | TIP1 | Pitch oscillation test concluded. Return to normal dwell mnemonic (Bus Voltage). |
|
| 07/05/2005 | 18:57:00 | | TIP to normal mode |
|
| 07/05/2005 | 17:20:00 | | Dwell on NRWAZMTI |
|
| 06/08/2005 | 07:06:00 | MIU | Clear out MIU errors and counters (CP MICLRERC) |
|
| 05/27/2005 | 22:20:00 | TIP1 | TIP low speed dwell changed to channel 297 (pitch Rwheel current). |
|
| 05/25/2005 | 17:30:00 | MIU | Enable MIU bus controller, nominal operation. MIU operational. |
|
| 05/25/2005 | 16:05:00 | MIU | Toggle MIU off then back on and reload patch. Operation successful. |
|
| 05/25/2005 | 12:45:00 | MIU | MIU powered on and patch loaded. |
|
| 05/20/2005 | 11:56:10 | DDR5B | DDR-5 turned on and operating nominally |
|
| 05/20/2005 | 11:56:00 | DDR5A | DDR-5 turned on and operating nominally |
|
| 05/20/2005 | 11:55:50 | DDR4B | DDR-4 turned on and operating nominally |
|
| 05/20/2005 | 11:55:40 | DDR4A | DDR-4 turned on and operating nominally |
|
| 05/20/2005 | 11:55:30 | DDR3B | DDR-3 turned on and operating nominally |
|
| 05/20/2005 | 11:55:20 | DDR3A | DDR-3 turned on and operating nominally |
|
| 05/20/2005 | 11:55:10 | DDR1B | DDR-1 turned on and operating nominally |
|
| 05/20/2005 | 11:55:00 | DDR1A | DDR-1 turned on and operating nominally |
|
| 05/20/2005 | 11:51:20 | XSU1 | On orbit first use of XSU-1 |
|
| 05/20/2005 | 11:50:00 | MIRP | on orbit |
|
| 05/20/2005 | 11:50:00 | XSU2 | on orbit, not powered up, redundant component. |
|
| 05/20/2005 | 11:50:00 | TIP2 | on orbit, not powered up, redundant component |
|
| 05/20/2005 | 11:50:00 | AIP1 | on orbit, powered up |
|
| 05/20/2005 | 11:50:00 | AIP2 | on orbit, not powered up, redundant component |
|
| 05/20/2005 | 10:22:03 | TIP1 | On orbit |
|
| 05/20/2005 | 06:00:00 | DDR2A | DDR-2 turned on prelaunch to record boost data. |
|
| 05/20/2005 | 06:00:00 | DDR2B | DDR-2 turned on prelaunch to record boost data. |
|
| 06/28/2000 | 14:15:00 | AIP1 | AIP data selected for McMurdo telemetry reception and command test in preparation for upcoming NOAA-18 MIMU tests. |
|
| 06/28/2000 | 14:15:00 | XSU1 | STX4 configured for AIP data for McMurdo telemetry reception and command test in preparation for upcoming NOAA-18 MIMU tests. |
